**Job Description**
This position involves joining the imec PACTS department, specifically the TACOS team, in either Leuven, Belgium, or Cambridge, UK. The role focuses on accelerator architecture and memory sub-system pathfinding, quantifying system-level implications of imec’s compute roadmap alongside advanced AI-centric memory and packaging technologies. This includes exploring uArchitectural integration and modelling of dense 3D memories, novel AI memories for near/in-memory compute, and advanced 2.5D and 3D packaging, bridging the gap between technology and system design.
**Skills & Abilities**
• Experienced in RTL design flows (Verilog/VHDL/SystemVerilog), logic synthesis, and exposure to PnR flows (place & route, timing closure, power estimation).
• Skilled in modeling and simulation methodologies for exploring PPA at system/uArchitecture level (e.g., analytical modeling, cycle-accurate simulators, full system modelling, and/or custom simulation frameworks).
• Familiar with the challenges and opportunities of AI memories and understanding their role in next-generation AI/ML accelerators.
• Experience working in multi-disciplinary teams, ideally interacting with hardware designers, software engineers, and technology experts.
• Critical mindset, eager to explore new challenges and evolve with changing R&D demands.
• Comfortable with automation, scripting, version control, and CI/CD flows to ensure reproducible and scalable research.
• Constructive team player, eager to learn and use others’ expertise.
• Excellent English proficiency.
**Qualifications**
Required Degree(s) in:
• Electrical Engineering
• Computer Engineering
• Computer Science
**Experience**
Other:
• Relevant industrial or academic experience in digital hardware design, system modeling, and/or uArchitecture research.
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